The present technology relates to a CDR (Clock Data Recovery) circuit, a reception apparatus, and a communication system that are applicable to serial communication for receiving digital signals for example.
Generally, in serial data communication, data DT and clock CLK are transmitted in parallel from a transmitter 1 to a receiver 2 through a data line 3 and a clock line 4 as shown in FIG. 1.
Data DT and clock CLK are entered in the receiver 2 with a certain timing. The receiver 2 latches the input data with a transition timing of the input clock.
In this case, while the circuit configuration of the receiver 2 is simplified, high-speed data communication applications are difficult because a difference in wiring delay between data DT and clock CLK, if any, causes a timing shift for latching the input data.
In order to overcome this problem, a scheme called clock embedding is generally used in high-speed serial data communication.
Referring to FIG. 2, there is shown schematic diagram illustrating the clock-embedded transmission scheme.
In the clock-embedded transmission scheme, only data signal is transmitted from a transmitter 1A to a receiver 2A. Because no clock signal is transmitted, the above-mentioned problem of the difference in delay between the data and clock wirings does not occur.
In the receiver 2A, a CDR (Clock Data Recovery) circuit is arranged. This CDR circuit recovers a clock signal from a data train signal by use of the periodicity of data signal transitions. The receiver 2A latches the input signal by use of this recovered clock.
In order to adjust the frequency of a clock signal with reference to the transition point of data in executing clock recovery, the CDR circuit requires a data transition rate higher than a certain frequency. If the data transition rate is too low, no information for clock extraction is obtained, thereby disabling stable clock extraction.
Therefore, the serial signal transmission based on the clock embedded scheme using the CDR circuit must use a certain method to ensure that the bit transition rate in data will not become too small.
Referring to FIG. 3, there is shown a clock-embedded transmission scheme based on reference transition, one of the schemes for maintaining the bit transition rate.
This scheme is used in a technology disclosed in Japanese Patent No. 2863763.
In this scheme, a rising transition is inserted in every certain number of bits of signal data so as to always enter a clock transition into the receiver within certain intervals.
A scheme in which a falling edge is inserted instead of a rising edge into every certain periods also provides the substantially the same effect as that described above.
Further, there is also a scheme in which a rising edge or a falling edge is inserted in accordance with the value of a bit before a reference transition. Manchester encoding (refer to U.S. Pat. No. 4,100,541) is one type of this scheme.
Referring to FIG. 4, there is shown an example of a transmission signal based on Manchester encoding.
In the example shown in FIG. 4, it is seen that a bit transition always occurs once in every two bits. In a receiver based on Manchester encoding, this transition is used to simplify the configuration of the CDR circuit of the receiver.